In general, semiconductor memory devices are tested in a package and/or wafer level to judge whether defects exit therein. This is accomplished by storing data in memory cells and then reading the stored data from the memory cells. For example, test data is programmed in memory cells of a non-volatile memory device, and then a read operation is performed with a word line voltage varied. As a result of the read operation, this test is capable of measuring a threshold voltage distribution of memory cells. Defects of memory devices, such as a short circuit between cells, bit lines, or word lines, and the breaking of bit lines or word lines, can be judged by parsing the measured threshold voltage distribution. A program operation for this testing (hereinafter, referred to as a test program operation) is performed in the same manner as a normal program operation.
In common, an incremental step pulse programming (ISPP) scheme has been utilized to control the threshold voltage distribution precisely. With this ISPP scheme, as illustrated in FIG. 1, a program voltage Vpgm is stepwise increased as program loops of a program cycle are repeated. As is well known, each program loop includes a program period and a program verify period. The program voltage Vpgm is increased by a given increment ΔVpgm, and a program time tPGM is continuously maintained during each program loop. In accordance with the above ISPP scheme, a threshold voltage of a cell is increased by ΔVpgm during each program loop. For this, the increment of the program voltage has to be set small to obtain a narrow width of a threshold voltage distribution of finally programmed cells. As the increment of the program voltage decreases, the number of program loops of a program cycle increases. Accordingly, the program loop number may be determined to obtain an optimum threshold voltage distribution without limiting performance of a memory device.
Exemplary circuits for generating a program voltage according to the ISPP scheme are disclosed in U.S. Pat. No. 5,642,309 entitled “AUTO-PROGRAM CIRCUIT IN A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE” and KP laid-open No. 2002-39744 entitled “FLASH MEMORY DEVICE CAPABLE OF PREVENTING PROGRAM DISTURB AND METHOD OF PROGRAMMING THE SAME”.
For measuring the threshold voltage distribution of memory cells in order to judge whether defects exist, it is unnecessary to control the threshold voltage distribution tightly. This is because a test operation is carried out to confirm whether memory cells are normally programmed or whether programmed memory cells are incorrectly judged as erased memory cells, rather than judging whether memory cells exist in a desired threshold voltage distribution. Shortening the test time means increased productivity. Accordingly, for performing the test program operation in the same manner as the normal program operation, the time needed to program memory cells during the test program operation is identical to that during the normal program operation. Also, during the test program operation the program voltage is generated in the same manner as that of the normal program operation. Thus it is difficult to shorten the time taken during the test program operation. However, it is possible to improve the productivity by shortening this time required to program memory cells during the test program operation.